1. Field of the Invention
This invention relates generally to the analysis of digital circuit designs and more specifically to protecting proprietary circuit designs from being decoded and reproduced.
2. Description of the Related Art
Manufacturers and users of digital circuitry design, analyze, and test proposed designs in accordance with well known methods for optimizing both physical location of system elements and overall timing characteristics, among other parameters. The design of large ASICs can be extremely complex, time consuming, and expensive, and the tasks of creating an optimal timing arrangement, minimizing overall wire length, and creating a logical design layout frequently require many man hours.
Circuit designers are frequently called upon to design circuits for highly specialized applications. Such circuits may be produced in extremely limited quantities, making the cost of the circuits to the user, or customer extremely high in order to justify the design costs. The inherent risk specialty chip designers face is that persons may obtain these design descriptions and wish to reverse engineer the designs, thereby having the ability to appropriate the designs without incurring the expenses associated with development and design.
A necessary obstacle all manufacturers face is that they must provide users with circuit design descriptions so that both the manufacturer and the user can analyze, evaluate and verify the overall performance of the circuit model under different conditions and in connection with different factors. The designer and user are frequently concerned with circuit timing, and thus both the designer and user analyze timing using various methods at different stages of development.
A timing analysis attempts to ensure that all component timing constraints will be satisfied during normal operation of the design. The constraints may include, for example, setup and hold times for an element, and write enable timing to address a storage device, such as RAM. Timing analyses are critical to the ultimate performance of the circuit.
A timing analysis also verifies that all high level timing specifications for the circuit design have been met. These timing specifications may include cycle time and I/O timing. Timing analysis aids the manufacturer-designer and the client-user in solving any problems associated with timing, and gives a manufacturer-designer and client-user a level of confidence that the design will perform properly under certain known situations. Timing analysis also provides a means for easily and quickly analyzing different potential problem solutions without requiring a full hardware design implementation.
The analysis aids both the manufacturer-designer and the client in designing a circuit which is fast enough to meet a cycle time requirement, or selecting a range of circuit elements which will result in fast and accurate operation under specified conditions.
Two common methods for performing timing verification are the static timing analysis and the dynamic timing analysis. The dynamic timing analysis requires the design of exhaustive input stimuli to simulate circuit functionality and thus is inappropriate for early analysis and evaluation of the design. A static timing analysis generally entails determining the critical paths in the design and analyzing the delays associated with these critical paths without the need for input stimuli. The designer or user performing a static timing analysis requires no pattern stimulation to accomplish the task and does not require computer simulation, as are needed in dynamic timing analyses. A designer or user can typically perform a static timing verification in one pass, thereby requiring little computer time.
As may be readily appreciated, a client or user wanting to perform a static timing analysis needs information about the design to accurately assess system performance. The manufacturer must therefore provide the client with the system design in order to determine system performance, typically by way of presenting the user with a gate level netlist of the connections between the elements utilized in the design.
The problem with providing the system design is that all the valuable information included in the design is out of the control of the manufacturer. The manufacturer must give a product which may have taken many man hours to complete with essentially no protection for the valuable proprietary information.
It is therefore a primary object of this invention to provide means for having a client or other user perform a static timing analysis in connection with its own configuration without providing the user with a fully functional design. It is an object of the invention to prevent the appropriation of an integrated circuit design, reproduction of the design, and the avoidance of the typical design costs associated with fabrication of the circuit.